You may have noticed quite a lot of buzz around RISC-V in tech news over the last few years. There are a few reasons for this, but first of all, what is this RISC-V thing anyway?!
RISC-V is an open standard instruction set architecture (ISA) that’s starting to gain in popularity to the point it’s now considered a viable alternative to ARM and x86. It’s especially suited to applications that require low power consumption and high performance, like Edge computing, embedded systems, and IoT.
So why the buzz? Well, the beauty of RISC-V is that it’s an open-source architecture, meaning it can be freely used and modified by anyone. This has led to a growing community of developers and engineers who are working to push the limits of what’s possible with RISC-V. And it’s not just academics who are getting involved either. Many of the biggest names in tech, including Apple, Nvidia, and Western Digital, have announced plans to investigate the use of RISC-V in their product lines. Another driving factor is the rise of the Internet of Things (IoT). As more and more devices become connected to the internet, there is a growing need for low-power, high-performance processors that can handle the demands of these devices. However, its uses are really much wider than this.
Introducing RISER: RISC-V for Cloud Services
CloudSigma is excited to announce we are participating in RISER, a new research and innovation project under the Horizon Europe program, funded by the European Commission. The project kicked off in January 2023 and will continue for the next 3 years.
RISER will develop the first all-European RISC-V cloud server infrastructure, significantly enhancing European Commission’s trade policy for open strategic autonomy. RISER will leverage and validate open hardware high-speed interfaces combined with a fully-featured operating system environment and runtime system, enabling the integration of low-power components, including RISC-V processor chips from the EPI and EUPILOT projects, in a novel energy-efficient cloud architecture.
EPI and EUPILOT processors floorplan
Two cloud-focused platforms
The RISER project will develop the following two cloud-focused platforms:
- An accelerator platform, which includes the Arm RHEA SoC from EPI and a PCIe acceleration board to be developed within the project, and will integrate up-to four RISC-V-based chips from EUPILOT.
PCIe Acceleration board block diagram
- A microserver platform, interconnecting up to ten microserver boards all developed by the project, each one supporting up to four RISC-V chips coupled with high-speed storage and networking. Embracing hyper-convergence, our microserver architecture allows for distributed storage and memory to be used by any processor in the system with low overhead. The open-source system board designs of RISER will be accompanied by low-level open-source firmware and systems software and a representative Linux-based software stack to support cloud services, facilitating uptake and enhancing the commercialization path of project results.
Indicative Microserver board block diagram
Three use cases will be developed to evaluate and demonstrate the capabilities of RISER platforms:
- Acceleration of compute workloads;
- Networked object and key-value storage;
- Containerized execution as part of a provider-managed IaaS environment.
The RISER architecture is organized into three main logical layers and related Work Packages to deliver an all-European open-source and open standard-based software and hardware integrated system.
- The Hardware Platforms layer, which includes an FPGA-based emulation infrastructure, a PCIe accelerator and a microserver.
- The System Software layer, which includes the required software infrastructure for booting and controlling the hardware, accessing the hardware peripherals and providing the execution environment for the cloud applications and services.
- The Use Cases layer, which includes the three use cases that will be used for the evaluation of the RISER platforms. RISER has a direct exploitation path to the contemporary proposals in the call, named “VITAMIN-V”, “AERO” and “OpenCUBE”, and we will design the RISER architecture with that in mind.
RISER Architecture logical layers
RISER brings together 7 partners from industry and academia to jointly develop and validate open-source designs for standardized form-factor system platforms, suitable for supporting cloud services.
Project coordinator: Manolis Marazakis, Foundation for Research and Technology – Hellas (FORTH)
Project website: https://www.riser-project.eu/
Project Twitter channel: @RiserProject
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